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8cb3ace92f
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8cb3ace92f | ||
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46f0202222 | ||
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7d274da197 | ||
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a3240d9316 | ||
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c92ccd41ce |
+1
-1
@@ -357,7 +357,7 @@ fs_node_t *fat16_open_at(const fs_node_t *directory, uint16_t index, uint64_t fl
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ei++;
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}
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fs_node_t *result = ei < entries_count ? open_entry(dir_cluster, entries, ei) : NUL;
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fs_node_t *result = open_entry(dir_cluster, entries, ei);
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memory_free(entries);
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+5
-14
@@ -538,7 +538,7 @@ uint64_t xhci_control_transfer(xhci_slot_t slot, uint64_t setup, void *data, uin
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}
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xhci_endpoint_t xhci_open_endpoint(xhci_slot_t slot, uint8_t address, uint8_t type, uint16_t max_packet_size, uint8_t interval) {
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LOG_LN_STEP("Opening endpoint slot %d address %hhx...", slot, address);
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LOG_LN_INFO("Opening endpoint slot %d address %hhx...", slot, address);
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ASSERT(slot < MAX_SLOTS, "xhci_control_transfer: Slot does not exist.");
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ASSERT(tsf_r_attached_slot == slot, "xhci_open_endpoint: Slot is not attached.");
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@@ -549,11 +549,11 @@ xhci_endpoint_t xhci_open_endpoint(xhci_slot_t slot, uint8_t address, uint8_t ty
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uint8_t ep_dir = (address >> 7) & 1;
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uint8_t dci = ep_num * 2 + ep_dir;
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LOG_LN_STEP("Setting up endpoint ring...");
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LOG_LN_INFO("Setting up endpoint ring...");
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RING_WRAP(ep);
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XHCI_TRB_CYCLE_W(&ep_r[RING_LENGTH], ep_r_cycle);
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LOG_LN_STEP("Configuring endpoint...");
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LOG_LN_INFO("Configuring endpoint...");
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memory_set(0, sizeof(xhci_input_ctx_t), &input_ctx);
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input_ctx.slot = device_ctx.slot;
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input_ctx.control.add_flags = (1 << 0) | (1 << dci);
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@@ -597,10 +597,9 @@ uint16_t xhci_read_endpoint(xhci_slot_t slot, xhci_endpoint_t endpoint, uint16_t
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XHCI_TRB_TRB_TYPE_W(ere, XHCI_TRB_TYPE_TRANSFER_NORMAL);
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XHCI_TRB_IOC_W(ere, 1);
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XHCI_TRB_CYCLE_W(ere, ep_r_cycle);
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RING_ADVANCE(ep);
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}
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ep_r_cycle ^= 1;
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db_regs[tsf_r_attached_slot] = ep_r_attached_endpoint;
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return 0;
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@@ -608,14 +607,6 @@ uint16_t xhci_read_endpoint(xhci_slot_t slot, xhci_endpoint_t endpoint, uint16_t
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uint16_t transferred = 0;
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while (XHCI_TRB_CYCLE_R(&evt_r[evt_r_i]) == evt_r_cycle && !transferred) {
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if (ep_processed_events == 0) {
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// A bit of a hack: flip link TRB cycle only after the first event is processed. There is some delay between controller
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// posting the last success event of the batch, and consuming the link TRB. Flipping the link cycle together with the batch
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// might happen before the controller got a chance to check the link cycle, and stall the consumption. If we received the
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// first event of the next batch, we're certain the link TRB has just been processed, and there's plenty of time before the next loop.
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XHCI_TRB_CYCLE_W(&ep_r[RING_LENGTH], !ep_r_cycle);
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}
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xhci_trb_t *cmp = &evt_r[evt_r_i];
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if (XHCI_TRB_TRB_TYPE_R(cmp) != XHCI_TRB_TYPE_EVENT_TRANSFER_COMPLETION) {
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@@ -657,7 +648,7 @@ uint16_t xhci_read_endpoint(xhci_slot_t slot, xhci_endpoint_t endpoint, uint16_t
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}
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void xhci_close_endpoint(xhci_slot_t slot, xhci_endpoint_t endpoint) {
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LOG_LN_STEP("Closing endpoind %hhx...", endpoint);
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LOG_LN_INFO("Closing endpoind %hhx...", endpoint);
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ASSERT(slot < MAX_SLOTS, "xhci_control_transfer: Slot does not exist.");
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ASSERT(tsf_r_attached_slot == slot, "xhci_close_endpoint: Slot is not attached.");
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@@ -5,7 +5,7 @@
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#define BLOCK_SIZE 65536
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exit_code_t pass(uint64_t fd) {
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static char buffer[BLOCK_SIZE];
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char buffer[BLOCK_SIZE];
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uint64_t bytes;
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while ((bytes = read(fd, BLOCK_SIZE, buffer))) {
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if (bytes == (uint64_t)-1) {
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@@ -6,7 +6,7 @@
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#define BLOCK_SIZE 65536
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exit_code_t pass(uint64_t fd) {
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static char buffer[BLOCK_SIZE];
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char buffer[BLOCK_SIZE];
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uint64_t bytes;
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uint64_t total = 0;
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while ((bytes = read(fd, BLOCK_SIZE, buffer))) {
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